The invention relates to a thin film transistor (TFT), and more particularly to an improved thin film transistor mainly. used for a load device of static random access memories (SRAMs) or liquid crystal displays (LCDs).
In recent years, thin film transistors (TFTs) including a thin film semiconductor are likely to be considered. Especially such thin film transistors has successfully been applied to load devices of the static random access memories (SRAMS) or switching devices in an active matrix circuitry for liquid crystal displays (LCDs).
The prior art thin film transistor, or an upper gate (coplanar) type thin film transistor will now be described with reference to FIG. 1. A silicon substrate 1 is prepared and a silicon oxide film 2 is formed on the silicon substrate 1. Subsequently, a polycrystalline silicon film is deposited on the silicon oxide film 2. By using normal processes for MOSFETs, a gate oxide film 7, a channel region 6, a gate electrode 8, source and drain regions 3 and 4 and an insulation film 9a are formed to complete the prior art thin film transistor. For those processes, the polycrystalline silicon film is subjected to an ion-implantation by using the gate electrode 8 as a mask thereby resulting in formations of self-aligned source and drain regions 3 and 4. Concurrently, the channel region 6 is defined by the source and drain regions 3 and 4 so that the channel region 6 is aligned directly under the gate electrode 8.
A bottom gate type thin film transistor will be described with reference to FIG. 2. A silicon substrate 1 is prepared and a silicon oxide film 2 is formed on the silicon substrate 1. After that, a gate electrode 8 made of polycrystalline silicon and a gate oxide film 7 are formed in turn. Subsequently, a polycrystalline silicon film is deposited on the gate oxide film 7. The polycrystalline silicon film is subjected to an ion-implantation by using a photoresist as-a mask so that source and drain regions 3 and 4 are formed. Concurrently, a channel region 6 is defined by the source and drain regions 3 and 4. As a result of those, the channel region 6 is provided directly over the gate electrode 8. Further, an insulation film 9a is deposited on the source, drain and channel regions 3, 4 and 6, after which a heat treatment is accomplished to complete the thin film transistor.
By the way, it is desired that such thin film transistors possess a reduced leakage current and a higher driving ability. To realize these characteristics, the channel region 6 requires a high quality polycrystal of a semiconductor thin film, for which a laser annealing for recrystallization or an electron beam annealing has been used to improve the quality of polycrystal. It should, however, be considered that such crystallization techniques have not been established under the existing circumstances in mass production, at appropriate cost and reproduction of the device.
Generally, amorphous silicon and polycrystalline silicon are used in a channel region formed of a semiconductor thin film. The polycrystalline silicon thin film which has previously been utilized is likely to be suitable to realize a higher performance thin film transistor rather than the amorphous silicon thin film. Nevertheless, the polycrystalline silicon film comprises the large number of crystal grains, each of which tends to include many crystal defects such as a twin crystal, which is undesirable. Such crystal defects cause the leakage current to be increased. In addition, such crystal defects and rough surfaces of the film also cause the drift mobility of carriers to be reduced. Those make performance characteristics of the thin film transistor inferior.